1. Field
Example embodiments of the following description relate to a hardware acceleration apparatus, method and computer-readable medium efficiently processing multi-core synchronization and that may store a lock variable in a shared memory, instead of repeatedly performing a spinning operation to acquire the lock variable, to improve a performance of a system with a minimum cost.
2. Description of the Related Art
Multi-core technologies enable integration of multiple processor cores in a single chip, to achieve high performance while using low power. A multi-core chip may be used in a large number of electronic devices.
When each algorithm constituting an application program is divided among multiple cores, a multi-core synchronization is used to synchronize the cores or to transmit or receive data.
To scalably increase performance of a multi-core system, it is most important to efficiently perform multi-core synchronization.
A spinlock is the most basic function of the multi-core synchronization.
A lock variable is stored in a shared memory to control an access to a shared resource, and only a core that acquires a lock using a spin_lock( ) function may exclusively use a corresponding resource.
A core that fails to acquire the lock waits for a backoff delay and repeatedly attempts to acquire the lock until the lock is acquired.
A core possessing the lock may return a lock variable through a spin_unlock( ) function.
In a spinlock scheme, the backoff delay may be estimated using software in order to improve performance.
Various schemes of estimating delay are provided, for example a simple scheme of using a constant delay, or a complicated scheme of appropriately adjusting the delay based on a history. Generally, an exponential backoff scheme (Delay′=Delay*2) is known to be the most efficient scheme.